As semiconductor wafers, silicon wafers made of single crystal silicon and bulk wafers made of compound semiconductor such as GaAs (hereinafter may be simply referred to as “bulk wafers”) are known. Also known are bonded wafers wherein an insulating film is provided on a surface of a bulk wafer and the bulk wafer is bonded to an active layer wafer with the insulating film. In such a bonded wafer, typically, the active layer wafer is further thinned to form an active layer, which is used as a semiconductor device formation area. Active layer wafers may or may not be of the same type of wafer as bulk wafers.
Particularly recently, SOI wafers having an SOI (silicon-on-insulator) structure have attracted attention in the fields of highly integrated CMOS devices and high breakdown voltage devices, as well as in the field of image sensors. The SOI wafer sequentially includes, on a support substrate, an insulating film such as silicon oxide (SiO2) film and a semiconductor layer such as a single crystal silicon layer used as a device active layer. While bulk silicon substrates have a relatively large parasitic capacitance that may be generated between the device and substrate, SOI wafers can significantly reduce the parasitic capacitance and therefore are advantageous in increasing the device speed, increasing the device breakdown voltage, reducing the device power consumption, etc.
In some cases, bonded wafers such as SOI wafers have a region called “terrace” formed around the outer periphery of the active layer for various purposes, such as preventing chipping. Further, a portion where such a terrace is provided (terrace portion) may be used for wafer handling in a device forming process for fabricating semiconductor devices in a bonded wafer.
By way of example, PTL 1 discloses an SOI wafer 900 wherein, as shown in FIG. 1, an active layer 930 made of silicon is provided on a support substrate 910 formed of a Si wafer with a silicon oxide film 920. In the SOI wafer 900, the outer peripheral edge of the active layer 930 is located more inward than the outer peripheral edge of the support substrate 910, and the peripheral edge of the active layer 910 is chamfered. Further, a terrace surface TA of the SOI wafer 900 is provided on the support substrate 910. Hereinafter, a flat surface region at an outer peripheral portion of a support substrate will be referred to as a terrace surface TA, and a slope surface between a flat surface of an active layer and the terrace surface TA will be referred to as a terrace slope surface TB. Hereinafter, the terrace surface TA and the terrace slope surface TB may be collectively referred to as a “terrace portion.”
The technique of PTL 1 makes it possible to prevent chipping at the bonded surface between the support substrate 910 and the active layer 930 or at the peripheral edge of the active layer 930 when the SOI wafer 900 is subjected to a device forming process.
In PTL 1, the following machining is performed in order to form the terrace portion described above. First, while rotating a bonded substrate prior to machining that is held on a wafer clamping table, the bonded substrate is brought close to a diamond electrodeposited surface of a chamfering wheel. By lifting or lowering the wafer clamping table to bring the bonded substrate in contact with a recessed surface, including a slope surface, of the chamfering wheel, a machined surface is then formed at the peripheral portion of each of the support substrate silicon wafer and the active layer silicon wafer.